BIST Scheme for Low Heat Dissipation and Reduced Test Application Time

This paper presents a simple yet efficient low hardware overhead testing scheme for scan-based built-in self-test (BIST) architecture that reduces switching activity (SA) in CUTs and test application time without compromising in the fault coverage. First demonstrated is the low transition LFSR (LT-LFSR) based test-per-scan scheme targeted for low heat dissipation during test by reducing the number of transitions at the cost of reduced fault coverage. Further explained is a proposed combined approach using both test-per-scan and test-per-clock application schemes, adding above LT-LFSR as the TPG and MISR for signature analysis. Experiments conducted on different ISCAS89 benchmark circuits shows that proposed scheme gives quite better fault coverage, that too, with a large reduction in test lengths and transitions (hence heat dissipation during testing)