Analysis and implementation of hierarchical real-time architectures

Multiprocessor architectures for real-time applications in signal processing and control are described. An investigation of these architectures to determine their performance under a variety of applications and task mixes is presented. The goal is to develop tools for configuring applications on multiple processor systems so that real-time constraints are met. The approach used is to solve queueing models that have been verified by empirical measurement of critical parameters taken during actual operation of the systems. Results relating to contention for bus use in the system are shown