Simultaneous Placement and Buffer Planning for Reduction of Power Consumption in Interconnects and Repeaters

Due to shrinking process geometries and an increasing number of chip components in very deep sub-micron technologies, interconnects emerged as a main limiting factor for performance, die area, and power consumption. Buffer allocation, interconnect congestion, power dissipation in buffered interconnects pose tremendous difficulties on the design process. It is therefore of paramount importance to address interconnect and buffer planning at early stages in the design flow, especially from the perspective of power consumption and thermal management. The goal of this work is to indicate the remarkable opportunities in reducing power consumption in buffered interconnects during placement, and to extend a classical placement algorithm to include power-optimized interconnect and buffer planning. The authors merge a placement algorithm based on simulated annealing with A-tree construction, van Ginneken´s buffer insertion algorithm, and accurate moment-based delay computation. The authors show that dramatic improvements can be achieved in terms of total interconnect structure capacitance and total area of required buffers