A New Test Generation Model for Broadside Transition Testing of Partial Scan Circuits

This paper proposes a new test generation model for broadside transition testing of partial scan circuits. In the proposed scheme, given a partial scan circuit whose kernel circuit is acyclic, the kernel circuit is transformed into some combinational circuits which are called broadside test generation models. These circuits are constructed by using a time-expansion model of the kernel circuit. All the broadside transition tests are generated by performing constrained stuck-at test generation on the transformed circuits. This means that, without developing a special test generation tool, existing combinational stuck-at test generation tools can be used to generate broadside transition tests for partial scan circuits. Experimental results show that the proposed scheme can reduce area overhead compared with the fully enhanced scan and full scan methods, and can generate broadside transition tests in reasonable test generation time