Improving ATPG Gate-Level Fault Coverage by using Test Vectors generated from Behavioral HDL Descriptions

Current hardware design flows include test pattern generation as a single step to be performed only after logical synthesis. However, early generation of few high level test patterns can provide higher test quality and reduce ATPG effort. In this work, the authors apply a software engineering technique for control flow based path testing, to extract test vectors from the behavioral HDL description of digital circuits. The authors show how one can adapt this software testing approach to test hardware devices. Experimental results show that combining high level generated test vectors with gate level ATPG can improve test quality, either increasing fault coverage and/or reducing test set size