Advanced SPICE-modelling of 6H-SiC-JFETs including substrate effects

This work presents an expression for the drain source current I _D, suitable for SPICE simulations of a 6H-SiC-JFET with an implanted gate area. Due to the lack of semi-insulating 6H substrates, such a JFET is influenced by the gate- and the substrate-channel-pn-junction and cannot be described with common JFET SPICE models. Accurate modeling is achieved by introducing a saturation voltage parameter α(V_GS) similar to that used for the description of GaAs-MESFETs (V_GS=gate source voltage). The applicability of the model is demonstrated using measurements on 6H-SiC-JFETs fabricated by Daimler Bent AG, Frankfurt. Even characteristics measured at 400°C are successfully modelled