Title :
Self-calibrating hybrid analog CMOS co-site interference canceller
Author :
Kub, F.J. ; Justh, E.W. ; Lippard, B.
Author_Institution :
Naval Res. Lab., Washington, DC, USA
fDate :
6/21/1905 12:00:00 AM
Abstract :
A continuous-time analog CMOS adaptive processor circuit is combined with high-power linear attenuators to implement a self-calibrating co-site interference canceller that achieves >40 dB cancellation for a +14 dBm interference level over a 30-88 MHz band. The analog CMOS adaptive processor implements the least mean square (LMS) error learning algorithm. A CMOS interference canceller is also demonstrated that is capable of cancelling multiple interfering signals simultaneously. The multiple interference CMOS co-site canceller demonstrated a frequency of operation of 80 MHz, an adaptivity of 60 dB, a minimum notch width of 25 kHz, a minimum adapt time constant of 25 μs, and the simultaneous cancellation of two CW interferers
Keywords :
CMOS analogue integrated circuits; UHF integrated circuits; adaptive signal processing; analogue processing circuits; hybrid integrated circuits; interference suppression; least mean squares methods; radiofrequency interference; 25 kHz; 25 mus; 30 to 88 MHz; 80 MHz; CMOS circuit; CW interferers; L-band; LMS error learning algorithm; UHF; continuous-time analog adaptive processor; high-power linear attenuators; hybrid analog co-site interference canceller; interference level; least mean square; minimum adapt time constant; minimum notch width; multiple interfering signals cancellation; CMOS analog integrated circuits; CMOS process; Frequency; Interference cancellation; Laboratories; Least squares approximation; Signal processing; Transmitters; VHF circuits; Voltage;
Conference_Titel :
Military Communications Conference Proceedings, 1999. MILCOM 1999. IEEE
Conference_Location :
Atlantic City, NJ
Print_ISBN :
0-7803-5538-5
DOI :
10.1109/MILCOM.1999.821363