A unified framework for characterizing retiming and scheduling solutions

Retiming and scheduling are two important techniques used in high-level synthesis. The interaction between these techniques is important for high-quality ASIC design; however, these techniques are often studied separately. In this paper, we systematically study retiming, scheduling, and the interaction between them. We begin with a characterization of all retiming solutions. A similar characterization is then given for scheduling solutions, and this characterization takes into account the interaction between retiming and scheduling. The contribution of this paper is two-fold: first, we believe that our method of characterizing retiming and scheduling solutions lends insight into these problems and how they interact. Second, we demonstrate an algorithm which can generate all possible retiming or scheduling solutions, allowing a circuit designer to explore the space of possible implementations for a given data-flow graph