Self aligned doping of mesa sidewalls for SOI transistors

Summary form only given. Lateral isolation of individual circuit components in CMOS/SOI technology is most effectively accomplished by creating mesa structures in the top silicon film. This construction results in a parasitic transistor at the edge of the silicon mesa which produces a hump in the subthreshold I-V characteristics and can result in added leakage current. The effects of the parasitic transistor can be eliminated if its threshold voltage is made higher than that of the main transistor by appropriate doping of the sidewall. However, this selective doping is not easily achieved, particularly if the sidewall edges are vertical. An improved technique has been developed for self-aligned doping of the sidewall transistor that uses the deposition and etch of a conformal oxide to pattern the doped sidewall region. This process sequence eliminates many of the problems associated with prior processes