A placement driven methodology for high-level synthesis of sub-micron ASIC´s

Author

Moshnyaga, Vasily G. ; Tamaru, Keikichi

Author_Institution

Dept. of Electron., Kyoto Univ., Japan

Volume

4

fYear

1996

Firstpage

572

Abstract

This paper proposes a novel methodology for automated data-path synthesis of deep submicron Application Specific Integrated Circuits (ASICs). In contrast to other approaches, we formulate interconnect area/delay optimizations as high-level synthesis transformations and use them during the synthesis to minimize impact of wiring on circuit characteristics. Experiments with 0.5 μm and 0.25 μm ASIC implementations of the DCT algorithm show that such formulation jointly with performance-driven floorplanning and “on-fly” module generation provides significant wiring delay reduction

Keywords

application specific integrated circuits; circuit layout CAD; high level synthesis; integrated circuit layout; 0.25 to 0.5 micron; DCT algorithm; automated data-path synthesis; deep submicron ASIC; delay optimizations; high-level synthesis; interconnect area optimizations; on-fly module generation; performance-driven floorplanning; placement driven methodology; submicron ICs; wiring delay reduction; Application specific integrated circuits; Delay effects; Fabrication; High level synthesis; Integrated circuit interconnections; Integrated circuit synthesis; Integrated circuit technology; Libraries; Synthesizers; Wiring;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1996. ISCAS '96., Connecting the World., 1996 IEEE International Symposium on

Conference_Location

Atlanta, GA

Print_ISBN

0-7803-3073-0

Type

conf

DOI

10.1109/ISCAS.1996.542088

Filename

542088