A processor interface model for fast system simulations

Author

Bolotin, Gary

Author_Institution

Jet Propulsion Lab., California Inst. of Technol., Pasadena, CA, USA

fYear

1993

Firstpage

519

Lastpage

522

Abstract

The author presents an alternative technique for performing board level simulations of designs involving processors. This technique requires only a standard C compiler and a few simulation library functions to perform accurate board level simulations. This method is currently being used to simulate the IBM 1750A based GVSC inter-subassembly bus (ISB) and ASICs that are being developed for the Cassini spacecraft. This method is superior to the conventional processor modeling techniques, which involve the use of detailed hardware modeling or extensive behavioral models

Keywords

application specific integrated circuits; circuit analysis computing; circuit layout CAD; hardware description languages; integrated circuit modelling; microprocessor chips; space vehicle electronics; system buses; ASIC; Cassini spacecraft electronics; GVSC inter-subassembly bus; VHDL; board level simulations; fast system simulations; hardware modeling; processor interface model; standard C compiler; Amplitude shift keying; Clocks; Computational modeling; Hardware; Laboratories; Process design; Propulsion; Registers; Software libraries; Space vehicles;

fLanguage

English

Publisher

ieee

Conference_Titel

ASIC Conference and Exhibit, 1993. Proceedings., Sixth Annual IEEE International

Conference_Location

Rochester, NY

Print_ISBN

0-7803-1375-5

Type

conf

DOI

10.1109/ASIC.1993.410772

Filename

410772