An improved architecture for the interconnections in a multi-chip CNN system

The design and realisation of reliable hardware CNN systems with a high number of cells is a key point in research in this field. On this topic, several different solutions have been proposed in VLSI implementations. In previously published papers, the authors presented current-mode interconnection-oriented integrated circuits to realise wide CNN networks. The multi-chip architecture shows the drawback to be a pad-limited structure because of the growing number of the pads required by the interconnections. In this paper a technique to improve the interconnection architecture without any lack of functionality will be presented. This approach will drastically cut the interconnection requirements by 75%. Some simulation results are presented together with experimental results