• DocumentCode
    1587889
  • Title

    A new model for general connectivity and its application to placement

  • Author

    Song, Jianjian ; Choo, Heng Kek ; Zhuang, Wenjun

  • Author_Institution
    Nat. Supercomput. Res. Center, Nat. Univ. of Singapore, Singapore
  • fYear
    1996
  • Firstpage
    60
  • Lastpage
    63
  • Abstract
    A new model for general connectivity is defined and its application to placement is presented in this paper. The new model is based on better understanding and analysis of connection graphs. Its computation time in the worst case is O(Nk+2), where N is the number of cells in a connection graph and k is the order of general connectivity. 41 placements for three circuits were carried out with our new model and the results are compared with those from the conductance model proposed by an earlier paper. Our new model is better than the conductance model because ours characterizes the connection graph more accurately, is faster to compute, and produces better results. The best performance improvements for the three circuits are 35.4% (HK5601), 37.8%(HK5852), and 19.2%(HK5851)
  • Keywords
    graph theory; integrated circuit layout; integrated circuit modelling; VLSI chip design; cell placement; computation time; connection graph; general connectivity; model; Chip scale packaging; Circuit optimization; Delay; Integrated circuit interconnections; Length measurement; Routing; Throughput; Very large scale integration; Wire; Wiring;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI, 1996. Proceedings., Sixth Great Lakes Symposium on
  • Conference_Location
    Ames, IA
  • ISSN
    1066-1395
  • Print_ISBN
    0-8186-7502-0
  • Type

    conf

  • DOI
    10.1109/GLSV.1996.497594
  • Filename
    497594