Title :
A high speed VLSI architecture for scaleable ATM switches
Author :
Shipley, Paul ; Sayed, Sherif ; Bayoumi, Magdy
Author_Institution :
Center for Adv. Comput. Studies, Southwestern Louisiana Univ., Lafayette, LA, USA
Abstract :
This paper presents a prototype of a VLSI chip to be used as a building block for an efficiently scaleable ATM switch with a link speed of 622.2 Mb/s. The chip is a 4×4 shared multibuffer ATM switch based on the distributing banyan architecture. It is efficient in storage space like a shared memory switch and scaleable in size like a space division switch. Since the architecture is self-routing, the chip contains all necessary routing control. Special high speed and low power circuitry is used. The chip is implemented in 1.0 micron static CMOS and measures only 25 mm2 in area
Keywords :
CMOS digital integrated circuits; VLSI; asynchronous transfer mode; electronic switching systems; multistage interconnection networks; telecommunication network routing; 1.0 micron; 622.2 Mbit/s; distributing banyan architecture; high speed VLSI architecture; link speed; low power circuitry; routing control; scaleable ATM switches; self-routing architecture; shared multibuffer switch; static CMOS; storage space; Asynchronous transfer mode; Buffer storage; CMOS technology; Communication switching; Computer architecture; Prototypes; Semiconductor device measurement; Space technology; Switches; Very large scale integration;
Conference_Titel :
VLSI, 1996. Proceedings., Sixth Great Lakes Symposium on
Conference_Location :
Ames, IA
Print_ISBN :
0-8186-7502-0
DOI :
10.1109/GLSV.1996.497596
