DocumentCode
1588022
Title
A provably good moat routing algorithm
Author
Cohoon, J.L. ; Cohoon, James P.
Author_Institution
Cadence Design Syst. Inc., San Jose, CA, USA
fYear
1996
Firstpage
86
Lastpage
91
Abstract
Moat routing is the routing of nets between the input/output pads and the core circuit. In this paper, it is proved that moat routing is NP-complete under the routing model in which there are no vertical conflicts and doglegs are disallowed (i.e., every net is routed within a single track). This contrasts with the fact that channel routing is efficiently solvable under these restrictions. The paper then presents an approximation algorithm for moat routing that computes moat routing solutions that are guaranteed to use at most four times the optimal number of tracks. Empirical results are presented indicating that for a number of industrial benchmarks, the algorithm produces solutions that are near optimal and that use significantly fewer tracks than previous moat routing strategies
Keywords
VLSI; circuit layout CAD; circuit optimisation; computational complexity; integrated circuit layout; network routing; NP-complete; VLSI; approximation algorithm; core circuit; industrial benchmarks; input/output pads; near optimal solutions; net routing; optimal track number; provably good moat routing algorithm; Approximation algorithms; Circuits; Computer science; Pins; Rivers; Routing; Terminology;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI, 1996. Proceedings., Sixth Great Lakes Symposium on
Conference_Location
Ames, IA
ISSN
1066-1395
Print_ISBN
0-8186-7502-0
Type
conf
DOI
10.1109/GLSV.1996.497599
Filename
497599
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