DocumentCode
1588237
Title
An implementation algorithm and design of a novel leading zero detector circuit
Author
Oklobdzija, Vojin G.
Author_Institution
Dept. of Electr. & Comput. Eng., California Univ., Davis, CA, USA
fYear
1992
Firstpage
391
Abstract
A novel way of implementing the leading zero detector (LZD) circuit is presented. The implementation is based on an algorithmic approach resulting in a modular and scalable circuit for any number of bits. This implementation is compared with the results obtained using modern logic synthesis (LS) tools in the same 0.9-μm CMOS technology. This approach to LZD design yields both speed and area advantages over LS
Keywords
CMOS integrated circuits; detector circuits; logic arrays; 0.9 micron; CMOS technology; LZD design; area; leading zero detector circuit; scalable circuit; speed; Algorithm design and analysis; CMOS logic circuits; CMOS technology; Circuit synthesis; Detectors; Hardware; Logic circuits; Logic design; Minimization; Registers;
fLanguage
English
Publisher
ieee
Conference_Titel
Signals, Systems and Computers, 1992. 1992 Conference Record of The Twenty-Sixth Asilomar Conference on
Conference_Location
Pacific Grove, CA
ISSN
1058-6393
Print_ISBN
0-8186-3160-0
Type
conf
DOI
10.1109/ACSSC.1992.269243
Filename
269243
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