Self-timed mesochronous interconnection for high-speed VLSI systems

Self-timed mesochronous interconnection scheme is presented for the interface between synchronous modules. It consists of a self-timed FIFO and a local clock control circuit placed between synchronous modules. The self-timed FIFO receives a data stream and holds it until the first data is synchronized at the receiving module. After the synchronization, the clock input to the receiving module is available through the local clock control circuit. The interconnection scheme operates regardless of the amount of the clock skew between the modules. An experimental design is presented that demonstrates the validity of the method