DocumentCode :
1588303
Title :
A study for optimum productivity yield in 0.16µm mixed of wafer fabrication facility
Author :
Chik, Mohd Azizi ; Yung, Ve Chun ; Balakrishna, Puvaneswaran ; Hashim, Uda ; Ahmad, Ibrahim ; Mohamad, Bashir
Author_Institution :
Inst. of Nanoelectronic Eng., Univ. Malaysia Perlis, Arau, Malaysia
fYear :
2010
Firstpage :
377
Lastpage :
380
Abstract :
This research is to study the opportunity to achieve optimum productivity yield in 0.16μm product mixed through understanding the impact of loading utilization towards the capacity. The study is important to model the overall strategy of product loading planning to get highest achievable product output at respective time like monthly or yearly. The product mixes target used in this analysis includes 0.20um to 0.13um for high voltage, logic CMOS and also mixed signal RF. Input in analysis are list of process flow for various technologies and products, major manufacturing activities and equipment configuration that is based on actual wafer fabrication facilities systems. Part of the complexities of the research is its long cycle time process from 45minutes to 9 hours, for respective same processing step that drives from varies technology and process equipment capable. Overall cycle time is from 30 days to 90 days that is various comparing product-to-product requirements. Further added to the complexity is the equipment used for this analysis that is more than 100 difference equipment configurations. More than 50% of the equipments are with difference configuration. Most products experienced re-entranced more than 85% times to same equipment type. This analysis done on generic semiconductor fab modeled using industries software, AutoSchedAP. The fab model configured intensively so match with exactly operation of the fab, with equivalent almost 100% manufacturing operation, product loading and tool configuration. The results have been successfully developed into a curve an equation shows the optimum product loading and gives opportunity of improvement in revenue and also overall efficiency of more than 10%. Further results of this study also summarized ranges of fab utilization versus cycle time that support overall product delivery. Other impacts are also discussed in the summary.
Keywords :
production engineering computing; production equipment; production facilities; production planning; productivity; semiconductor device manufacture; work in progress; AutoSchedAP; cycle time; equipment configuration; generic semiconductor fab model; industry software; loading impact; logic CMOS; manufacturing activities; manufacturing operation; mixed signal RF; optimum productivity yield; process equipment; process flow; product delivery; product loading planning; product output; product-to- product requirements; revenue; tool configuration; wafer fabrication facility; CMOS logic circuits; CMOS process; Fabrication; Productivity; RF signals; Semiconductor device modeling; Signal analysis; Signal processing; Strategic planning; Voltage; Cycle Time; Simulation; Work In Progress (WIP). Silicon Wafer Manufacturing Plan (Fab);
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Semiconductor Electronics (ICSE), 2010 IEEE International Conference on
Conference_Location :
Melaka
Print_ISBN :
978-1-4244-6608-5
Type :
conf
DOI :
10.1109/SMELEC.2010.5549356
Filename :
5549356
Link To Document :
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