Title :
Clock buffer placement algorithm for wire-delay-dominated timing model
Author :
Edahiro, Masato ; Lipton, Richard J.
Author_Institution :
C&C Syst. Res. Labs., NEC Corp., Kawasaki, Japan
Abstract :
A clock buffer placement algorithm is proposed for future technologies in which wire delay dominates signal delay. In such technologies, buffers need to be placed so as to minimize the maximum wire delay. We formulate the problem into a non-linear programming, and solve it by an iteration method with a randomized technique. We applied our buffer placement algorithm with a zero-skew router to several benchmark data, and show that our algorithm achieves 30% less delay time than a H-tree based algorithm
Keywords :
buffer circuits; clocks; delays; iterative methods; logic CAD; network routing; nonlinear programming; timing; benchmark data; clock buffer placement algorithm; delay time; iteration method; nonlinear programming problem; randomized technique; wire-delay-dominated timing model; zero-skew router; Clocks; Delay effects; Dynamic programming; Flip-flops; Laboratories; National electric code; Signal design; Timing; Topology; Wire;
Conference_Titel :
VLSI, 1996. Proceedings., Sixth Great Lakes Symposium on
Conference_Location :
Ames, IA
Print_ISBN :
0-8186-7502-0
DOI :
10.1109/GLSV.1996.497610
