Title :
CMOS transistor sizing for minimization of energy-delay product
Author :
Tretz, Christophe ; Zukowski, Charles
Author_Institution :
Dept. of Electr. Eng., City Univ. of New York, NY, USA
Abstract :
In this paper, we revisit three of the well known optimization results in CMOS transistor sizing with the energy-delay product as a new metric. We study the absolute sizes of and the ratio between n-channel and p-channel transistor widths in uniform logic, the optimal distance between repeaters in an RC line, and the optimum number of inverter stages, along with their sizes, needed to drive a large load capacitance. Results, both theoretical and numerical, show that in general the optimum solutions for energy-delay lead to smaller designs than the ones obtained for minimum delay
Keywords :
CMOS logic circuits; MOSFET; capacitance; circuit layout CAD; circuit optimisation; delays; integrated circuit layout; logic CAD; minimisation of switching nets; timing; CMOS transistor sizing; RC line; energy-delay product minimisation; inverter stages; large load capacitance; n-channel transistor width; p-channel transistor width; repeaters; CMOS logic circuits; Cost function; Delay effects; Energy efficiency; Inverters; Logic design; Logic gates; Power supplies; Semiconductor device modeling; Voltage;
Conference_Titel :
VLSI, 1996. Proceedings., Sixth Great Lakes Symposium on
Conference_Location :
Ames, IA
Print_ISBN :
0-8186-7502-0
DOI :
10.1109/GLSV.1996.497614
