DocumentCode
1588452
Title
Low-power implementation of discrete cosine transform
Author
Farag, Emad N. ; Elmasry, Mohamed I.
Author_Institution
VLSI Res. Group, Waterloo Univ., Ont., Canada
fYear
1996
Firstpage
174
Lastpage
177
Abstract
The demand for multimedia mobile terminals has created a need for low power implementation of video compression algorithms. In this paper we consider different implementations for the discrete cosine transform. The effect of pipelining and parallelism on reducing the power dissipation is considered for fast discrete cosine transform algorithms, as well as ROM-based algorithms
Keywords
VLSI; data compression; digital signal processing chips; discrete cosine transforms; parallel processing; pipeline processing; read-only storage; video coding; ROM-based algorithms; discrete cosine transform; fast DCT algorithms; low-power implementation; parallelism; pipelining; power dissipation reduction; video compression algorithms; Delay; Discrete cosine transforms; Mobile computing; Parallel processing; Pipeline processing; Power dissipation; Read only memory; Throughput; Video compression; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI, 1996. Proceedings., Sixth Great Lakes Symposium on
Conference_Location
Ames, IA
ISSN
1066-1395
Print_ISBN
0-8186-7502-0
Type
conf
DOI
10.1109/GLSV.1996.497615
Filename
497615
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