Title :
Low-power implementation of discrete cosine transform
Author :
Farag, Emad N. ; Elmasry, Mohamed I.
Author_Institution :
VLSI Res. Group, Waterloo Univ., Ont., Canada
Abstract :
The demand for multimedia mobile terminals has created a need for low power implementation of video compression algorithms. In this paper we consider different implementations for the discrete cosine transform. The effect of pipelining and parallelism on reducing the power dissipation is considered for fast discrete cosine transform algorithms, as well as ROM-based algorithms
Keywords :
VLSI; data compression; digital signal processing chips; discrete cosine transforms; parallel processing; pipeline processing; read-only storage; video coding; ROM-based algorithms; discrete cosine transform; fast DCT algorithms; low-power implementation; parallelism; pipelining; power dissipation reduction; video compression algorithms; Delay; Discrete cosine transforms; Mobile computing; Parallel processing; Pipeline processing; Power dissipation; Read only memory; Throughput; Video compression; Voltage;
Conference_Titel :
VLSI, 1996. Proceedings., Sixth Great Lakes Symposium on
Conference_Location :
Ames, IA
Print_ISBN :
0-8186-7502-0
DOI :
10.1109/GLSV.1996.497615
