TROY: a tree based approach to logic synthesis and technology mapping

In this paper we present a new approach to the synthesis of combinational circuits and the mapping of standard gates like NAND, NOR, AOI and OAI with arbitrary number of inputs. Our method is based on the provable optimal synthesis of the fan-out-free regions of a circuit, represented as normal AND-OR-trees. Normal AND-OR-trees enable TROY to rebalance the regions with respect to delay without loosing area and lead to a much larger search space than that used by tree matching. Fast heuristics derived from the optimal approach yield significantly faster results than SIS on many standard benchmark circuits