Title :
Transistor chaining in CMOS leaf cells of planar topology
Author :
Carlson, Bradley S. ; Chen, C. Y Roger ; Meliksetian, Dikran S.
Author_Institution :
Dept. of Electr. Eng., State Univ. of New York, Stony Brook, NY, USA
Abstract :
A technique for chaining the transistors in the layouts of static CMOS leaf cells is presented and analyzed. This new method is superior to existing techniques, since it can operate on a more general class of circuits and is very efficient. It is shown that the layout width of a CMOS leaf cell can be significantly reduced (nearly 40% in the average case) by transistor chaining. Moreover, more than half of the switching functions of four variables have optimal CMOS circuit implementations with non-series/parallel topologies. Therefore, the use of non-series/parallel circuits can have a positive global impact on layout area and performance. The transistor chaining technique presented in this paper produces the optimal solution for 82% of the circuits tested, and has linear time complexity
Keywords :
CMOS digital integrated circuits; VLSI; circuit layout CAD; graph theory; integrated circuit layout; network topology; switching functions; CMOS leaf cells; layout area; linear time complexity; nonseries/parallel circuits; optimal CMOS circuit implementations; planar topology; static cell layouts; switching functions; transistor chaining; Circuit synthesis; Circuit testing; Circuit topology; Design automation; Fusion power generation; Integrated circuit interconnections; Network topology; Switching circuits; Very large scale integration;
Conference_Titel :
VLSI, 1996. Proceedings., Sixth Great Lakes Symposium on
Conference_Location :
Ames, IA
Print_ISBN :
0-8186-7502-0
DOI :
10.1109/GLSV.1996.497619