C-V analysis of ultrathin DSPE SOS

Summary form only given. Capacitors have been fabricated in thinned double solid phase epitaxial (DSPE) silicon on sapphire (SOS). The silicon films are 100-nm thick and doped with phosphorus to 5e+16/cm ². The capacitor structures are gated Hall bars with a polysilicon gate on a 25-nm oxide with the source and drain doped N⁺. Capacitance data were taken with a lock-in amplifier at low frequencies. Experimental data indicated four regions in a thin-film C-V plot. Three of these regions are the classic accumulation, inversion, and depletion regions. The fourth region is unique to electrically thin films and is called the fully depleted region. The value of the capacitance in region four has been shown to depend quantitatively on the electrically active traps in thin SOS/SOI structures. Thus a thin-film capacitance voltage plot is a sensitive technique for measuring electrically active traps in SOI structures. A model has been developed that explains C-V plots on the thinned, as-purchased SOS and how that relates to C-V plots on the improved SOS. A computer simulation program was written to solve Poisson´s equation exactly and predict C-V plots using the proposed model. On the basis of the simulation, the trap model and data show very good agreement. Reduction of trap levels by a factor of 30 in the DSPE material has been measured