Phase noise optimization of CMOS VCO through harmonic tuning

Author

Ryu, Seonghan ; Chung, Yujin ; Kim, Huijung ; Choi, Jinsung ; Kim, Bumman

Author_Institution

Pohang Univ. of Sci. & Technol., South Korea

fYear

2005

Firstpage

403

Lastpage

406

Abstract

An optimization technique for a low phase noise CMOS LC VCO is proposed. The combination of harmonic tuning and on-chip filtering improves both 1/f³ and 1/f² phase noise more than 10 dB over a comparable reference VCO. A 2.7 V, 5.4 mA, 30% tuning range, 1 GHz voltage controlled oscillator (VCO) is designed with the technique and implemented in a 0.35 μm CMOS process. The optimized 1 GHz CMOS differential VCO achieves -89 dBc/Hz, -116 dBc/Hz and -135 dBc/Hz at 10 kHz, 100 kHz, and 1 MHz offset frequencies from the carrier, respectively.

Keywords

1/f noise; CMOS analogue integrated circuits; UHF oscillators; circuit optimisation; circuit tuning; flicker noise; harmonic oscillators (circuits); phase noise; voltage-controlled oscillators; 0.35 micron; 1 GHz; 1/f noise; 2.7 V; 5.4 mA; 800 MHz to 1.1 GHz; CMOS LC VCO; VCO phase noise optimization; differential VCO; flicker noise; harmonic tuning; on-chip filtering; tuning range; 1f noise; CMOS process; CMOS technology; Frequency; Integrated circuit noise; Noise shaping; Phase noise; Power harmonic filters; Tuning; Voltage-controlled oscillators;

fLanguage

English

Publisher

ieee

Conference_Titel

Radio Frequency integrated Circuits (RFIC) Symposium, 2005. Digest of Papers. 2005 IEEE

ISSN

1529-2517

Print_ISBN

0-7803-8983-2

Type

conf

DOI

10.1109/RFIC.2005.1489825

Filename

1489825