Author_Institution :
Integrated Products, Austin, TX, USA
Abstract :
Notice of Violation of IEEE Publication Principles
"A 9.953/10.7/12.5 GHz 0.13 μm CMOS LC oscillator using capacitor calibration and a VGs/R based low noise regulator"
by Maxim, A.
in the Proceedings of the 2005 IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, Digest of Papers.
12-14 June 2005 Page(s):411 - 414
After careful and considered review, it has been determined that the above paper is in violation of IEEE\´s Publication Principles.
Specifically, the paper contains information that Adrian Maxim admits had been falsified. In response to an inquiry on this misconduct, Mr. Maxim acknowledged that the following people who have been listed as co-authors on several of his papers are fabricated names and that he is the only author:
C. Turinici, D. Smith, S. Dupue, M. Gheorge, R. Johns, D. Antrik
Additionally, in papers by Mr. Maxim that have co-authors other than those listed above, it was discovered in some cases that he had not consulted with them while writing the papers, and submitted papers without their knowledge.
Although Mr. Maxim maintains that not all of the data is falsified, IEEE nevertheless cannot assure the integrity of papers posted by him because of his repeated false statements.
Due to the nature of this violation, reasonable effort should be made to remove all past references to the above paper, and to refrain from any future references.A low phase noise multi-rate OC192 LC oscillator was realized in 0.13 μm CMOS. To minimize the gain of the oscillator, the frequency is first calibrated to within ±0.1% of the target value using a capacitor switching network and then the final locking is achieved with a PLL loop that controls a ±1% tuning range accumulation MOS varactor bank. The oscillator uses an NFET-only, constant bias voltage amplifier that eliminates the tail current source. A high PSRR and low 1/f and thermal noise regulator, based on a - /sub GS//R current, was used to bias the oscillator. The LC-VCO specifications include: phase noise <-115 dBc/Hz at 100 kHz offset, 40 kHz 1/f/sup 3/ corner frequency, <10 mA current consumption from a 3.3 V supply and 250×400 μm/sup 2/ die area.
Keywords :
1/f noise; CMOS integrated circuits; MMIC amplifiers; MMIC oscillators; calibration; circuit tuning; phase locked loops; phase noise; switched capacitor networks; thermal noise; varactors; voltage regulators; voltage-controlled oscillators; 0.13 micron; 10 mA; 10.7 GHz; 12.5 GHz; 250 micron; 3.3 V; 400 mm; 9.953 GHz; CMOS oscillator; MOS varactor bank; NFET amplifier; PLL loop frequency locking; VCO; capacitor calibration; capacitor switching network; constant bias voltage amplifier; frequency calibration; high PSRR regulator; low 1/f noise regulator; low phase noise oscillator; low thermal noise regulator; multirate OC192 LC oscillator; spurs; tuning range; Calibration; Frequency; Integrated circuit noise; MOS capacitors; Notice of Violation; Oscillators; Phase noise; Radiofrequency integrated circuits; Switched capacitor networks;