A scan path selection method for RTL and mixed level circuits

In this paper we have presented a partial scan cost estimation technique for random testing. The primary objective of this approach is to give an early scan cost estimation to facilitate design iterations at the system level. There are three major assumptions in this work: 1) the effective randomness at the outputs of each module can be increased by increasing the number of random patterns at the inputs of the respective module. 2) The data interdependency at the outputs of each module can be broken by a proper cover (with a specified correlation threshold). 3) The fault propagation ability of each module can be approximated by the sensitivity of the respective module. The experimental results presented reveal the proposed methodology: a) to be applicable at RTL with fast turnaround time and reasonable errors; b) can help design engineers explore tradeoffs between test time, overhead, and fault coverage; and c) has the potential to apply to gate level circuitry