A digital signal processing chip for iterative deconvolution restoration algorithms

A VLSI DSP chip is presented that will significantly improve the processing throughput for a general class of iterative deconvolution algorithms. The design will be based on a systolic array concept. This will enable these algorithms to be used for real time DSP applications which formerly due to speed limitations were not possible. The increased class of applications will enable further understanding of these applications. The higher throughput will also enable the researcher to further take advantage of the features unique to iterative deconvolution