Title :
Design and VLSI implementation of a unified synapse-neuron architecture
Author :
Djahanshahi, H. ; Ahmadi, M. ; Jullien, G.A. ; Miller, W.C.
Author_Institution :
Dept. of Electr. Eng., Windsor Univ., Ont., Canada
Abstract :
We describe the design and VLSI implementation of a unified synapse-neuron architecture for multi-layer neural networks. A new hybrid building block proposed for this purpose is formed by integrating a partial S-shape neural nonlinearity within a Multiplying DAC synapse. MDAC synapse contains modifications to simplify sign-bit circuit. Small analog circuits generate a distributed S-shape neural function by combining quadratic characteristics of four MOS transistors. The proposed modular neural network architecture features design simplicity and scalability, area efficiency, reduced interconnection problem, improved robustness and digital programmability. Based on the proposed scheme, we have considerably increased the synaptic density in the improved version of a programmable optically-coupled neural network
Keywords :
VLSI; mixed analogue-digital integrated circuits; neural chips; neural net architecture; MOS transistors; VLSI; area efficiency; design; digital programmability; distributed S-shape neural function; hybrid digital-analog building block; interconnection; modular architecture; multilayer neural network; multiplying DAC synapse; partial S-shape neural nonlinearity; programmable optically-coupled network; quadratic characteristics; robustness; scalability; sign-bit circuit; synaptic density; unified synapse-neuron architecture; Analog circuits; Character generation; Integrated circuit interconnections; MOSFETs; Multi-layer neural network; Neural networks; Optical computing; Robustness; Scalability; Very large scale integration;
Conference_Titel :
VLSI, 1996. Proceedings., Sixth Great Lakes Symposium on
Conference_Location :
Ames, IA
Print_ISBN :
0-8186-7502-0
DOI :
10.1109/GLSV.1996.497624
