DocumentCode
1590087
Title
A variable sampling rate third order MASH ΣΔ modulator for measurement applications
Author
Baccigalupi, A. ; Piscopo, M.
Author_Institution
Dept. of Comput. Sci., Naples Univ., Italy
Volume
2
fYear
1998
Firstpage
1207
Abstract
The paper presents, analyzes and simulates the behaviour of a variable-sampling-rate, third order, sigma delta modulator based on switched capacitor integrators. Theoretical study, as well as simulations carried out on the model, shows the possibility to reach a S/N ratio allowing 17 equivalent bit resolution
Keywords
integrating circuits; sigma-delta modulation; switched capacitor networks; S/N ratio; resolution; switched capacitor integrators; third order MASH ΣΔ modulator; variable sampling rate; Circuit stability; Clocks; Delay; Delta modulation; Multi-stage noise shaping; Sampling methods; Switched capacitor circuits; Switches; Switching circuits; Timing;
fLanguage
English
Publisher
ieee
Conference_Titel
Instrumentation and Measurement Technology Conference, 1998. IMTC/98. Conference Proceedings. IEEE
Conference_Location
St. Paul, MN
ISSN
1091-5281
Print_ISBN
0-7803-4797-8
Type
conf
DOI
10.1109/IMTC.1998.676916
Filename
676916
Link To Document