DocumentCode
1590098
Title
A Redundancy Mechanism under Single Chip Multiprocessor Architecture
Author
Shi, Qingsong ; Chen Jian ; Zhang, Nan ; Cao, Mingteng ; Chen, Jian
Author_Institution
Coll. of Comput. Sci., Zhejiang Univ., Hangzhou
fYear
2008
Firstpage
249
Lastpage
254
Abstract
Chip multiprocessor (CMP) will become more popular in embedded systems. As clock frequency increases, dependency among core blocks rises, which therefore tends to reduce performance of system and be more unstable. Redundancy is a way to improve the dependability of the system. But the traditional methods cannot make full use of the computing capacity of CMP. In this paper, we propose a new redundancy mechanism. The whole system is reorganized using lightweight virtualization. A group of processors and a block of memory are treated as a single logical computing unit each of which corresponds to a processer separately. In this way, only a distributor and an arbiter need to be added into operating system with least effort. The distributor dispatches one task to all the logical computing units. After execution, the arbiter gathers all results to analyze whether they are dependable. Because the distributor and the arbiter are very simple, total overhead of the system are very low. Experiment results show the proposed method is practical with average overhead less than 8%.
Keywords
microprocessor chips; redundancy; software fault tolerance; lightweight virtualization; logical computing unit; redundancy mechanism; single chip multiprocessor architecture; Computer architecture; Distributed computing; Embedded system; Fault detection; Fault tolerance; Frequency; Hardware; Redundancy; Surface-mount technology; Yarn; CMP; Redundancy; Reliability;
fLanguage
English
Publisher
ieee
Conference_Titel
Embedded Computing, 2008. SEC '08. Fifth IEEE International Symposium on
Conference_Location
Beijing
Print_ISBN
978-0-7695-3348-3
Type
conf
DOI
10.1109/SEC.2008.29
Filename
4690757
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