• DocumentCode
    15902
  • Title

    Cost-Effective Robustness in Clock Networks Using Near-Tree Structures

  • Author

    Ewetz, Rickard ; Cheng-Kok Koh

  • Author_Institution
    Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN, USA
  • Volume
    34
  • Issue
    4
  • fYear
    2015
  • fDate
    Apr-15
  • Firstpage
    515
  • Lastpage
    528
  • Abstract
    Clock trees are commonly used to deliver clock signals to sequential elements in circuits. However, by construction, tree structures are inherently prone to failure caused by variations. The robustness of a clock tree can be improved by inserting redundancy in the form of cross links or multilevel fusion trees. Such near-tree structures can provide robustness at low cost. In this paper, we establish that the locations of the inserted redundancy are crucial in providing cost-effective robustness. We present two methods to systematically insert redundancy. The redundancy is realized by either inserting cross links or performing local merges. Moreover, we present a vertex reduction method that reduces the amount of redundancy that needs to be inserted in our near-tree structures. Empirical results show that our structures are more robust to variations and have lower power consumption compared to the state-of-the-art clock networks. Furthermore, our near-tree structures provide smooth trade-offs between cost and robustness, reducing clock skews by 11%-39% at an expense of 3%-68% higher power consumption.
  • Keywords
    clocks; low-power electronics; redundancy; sequential circuits; trees (mathematics); clock networks; clock signals; clock skews; clock trees; cost effective robustness; cross links; low power consumption; multilevel fusion trees; near-tree structures; redundancy insertion; sequential elements; vertex reduction; Capacitance; Clocks; Monte Carlo methods; Power demand; Redundancy; Robustness; Wires; Algorithms; clock network synthesis; low-power; physical design;
  • fLanguage
    English
  • Journal_Title
    Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0278-0070
  • Type

    jour

  • DOI
    10.1109/TCAD.2015.2391253
  • Filename
    7008465