Test generation for crosstalk effects in VLSI circuits

Crosstalk in VLSI circuits results from parasitic capacitances between interconnect lines. The more signal pathways close to each other on the chip, the greater the coupling effect. Most current timing analyzers, however, have not addressed the effect. We investigated two crosstalk effects: the Crosstalk Glitch (CTG) and the Crosstalk Delay (CTD). The CTG effect can be provoked when line drivers are unbalanced and the coupling capacitance is dominant over the ground capacitances. The signal duration of the CTG increases as the clock transition time decreases. The CTD effect can be provoked regardless of the balancing condition of the drivers. We developed an algorithm, ATEG (Automatic Test Extractor for Glitch), which can generate test vectors to activate and propagate CTG signals by employing several new techniques such as simultaneous gate input assignment, optimized backtracking, and dynamic signal transition tracing