An ESD protected RFIC power amplifier design

Author

Muthukrishnan, Swaminathan ; Zhao, Jian ; Studtmann, George ; Raman, Sanjay

Author_Institution

Dept. of ECE, Virginia Tech, Blacksburg, VA, USA

fYear

2005

Firstpage

605

Lastpage

608

Abstract

This paper presents the development of electrostatic discharge (ESD) protection circuitry for a three-stage power amplifier (PA) designed for 1.9 GHz digitally enhanced cordless telephone (DECT) applications. Through careful RF and ESD circuit co-design, good RF performance and ESD immunity are achieved. The PA features a high gain of 26 dB at an output power of 25 dBm, which remained unaffected due to the inclusion of ESD circuitry. The circuit´s power added efficiency (PAE) is also relatively unaffected, remaining at around 43%. The circuit is fabricated using a commercial 0.5 μm SiGe-HBT process. The design is capable of protecting the PA from -4 kV to +1.5 kV human body model (HBM) ESD stresses.

Keywords

Ge-Si alloys; UHF power amplifiers; bipolar integrated circuits; cordless telephone systems; electrostatic discharge; integrated circuit design; integrated circuit reliability; -4 to 1.5 kV; 0.5 micron; 1.9 GHz; 26 dB; DECT; ESD immunity; ESD protection circuitry; Ge-Si; LC tank; PAE; RF performance; RFIC power amplifier; SiGe-HBT process; circuit co-design; digitally enhanced cordless telephone; electrostatic discharge; human body model; power added efficiency; radio frequency integrated circuit; three-stage power amplifier; Electrostatic discharge; Gain; Immune system; Power amplifiers; Power generation; Protection; Radio frequency; Radiofrequency amplifiers; Radiofrequency integrated circuits; Telephony;

fLanguage

English

Publisher

ieee

Conference_Titel

Radio Frequency integrated Circuits (RFIC) Symposium, 2005. Digest of Papers. 2005 IEEE

ISSN

1529-2517

Print_ISBN

0-7803-8983-2

Type

conf

DOI

10.1109/RFIC.2005.1489886

Filename

1489886