DocumentCode :
1590685
Title :
Improvement of electrical characteristics in LDMOS by the insertion of PBL and gate extended field plate technologies
Author :
Minchin, Tsai ; Gene, Sheu ; Ruey, Tsai Jung ; Shaoming, Yang
Author_Institution :
Dept. of Comput. Sci. & Inf. Eng., Asia Univ., Taichung, China
Volume :
4
fYear :
2011
Firstpage :
5
Lastpage :
9
Abstract :
This article provides a fabricating method to improve significantly both of the breakdown voltage and specific on-resistance in high resistivity drift region LDMOS using by both of the PBL doping under the source terminal and the gate extended field plate technologies. The insertion of PBL aims at the reduction of bulk current caused by the impact-ionization-generated holes while the gate extended field plate were be used to shift the impact ionization region from N-drift region surface near the gate side down toward the junction between the P-body and N-drift region to increase the breakdown voltage due to the increase of maximum depletion in the N-drift region.
Keywords :
MOS integrated circuits; electric breakdown; N-drift region surface; P-body; PBL doping; breakdown voltage; bulk current; electrical characteristics; gate extended field plate technologies; high resistivity drift region LDMOS; impact ionization region; impact-ionization-generated holes; Doping; Electric fields; Impact ionization; Junctions; Logic gates; Performance evaluation; Semiconductor process modeling; LDMOS; TCAD simulation; breakdown voltage; field plate; impact ionization; on-resistance;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electronic Measurement & Instruments (ICEMI), 2011 10th International Conference on
Conference_Location :
Chengdu
Print_ISBN :
978-1-4244-8158-3
Type :
conf
DOI :
10.1109/ICEMI.2011.6037935
Filename :
6037935
Link To Document :
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