A 40-dBm OIP3, 2-GHz silicon bipolar LNA

Author

Motta, C. ; Girlando, G. ; Castorina, A. ; Palmisano, G.

Author_Institution

STMicroelectronics, Catania, Italy

fYear

2005

Firstpage

633

Lastpage

636

Abstract

A 2-GHz silicon bipolar LNA, based on a cascode architecture, implementing input and output matching networks, and designed to optimize matching, noise and linearity simultaneously, is presented. The LNA exhibits a gain of 18 dB, a noise figure of 1.6 dB and an OIP3 of +40 dBm, while consuming only 4 mA. To measure the linearity performance a non-conventional test-bench was developed. Statistical simulations and measurements were carried out on the LNA revealing a high sensitivity of the OIP3 to process variations. A technique to restore the linearity performance is also described.

Keywords

UHF amplifiers; UHF integrated circuits; bipolar analogue integrated circuits; circuit optimisation; integrated circuit design; integrated circuit noise; linearisation techniques; random noise; statistical analysis; 1.6 dB; 18 dB; 2 GHz; 4 mA; OIP3; Si; cascode architecture; gain; linearity optimization; low noise amplifiers; matching networks; matching optimization; noise figure; noise optimization; sensitivity; silicon bipolar LNA; statistical analysis; third order output intercept point; Circuit noise; Circuit testing; Distortion measurement; Frequency; Impedance matching; Linearity; Noise figure; Power dissipation; Radiofrequency amplifiers; Silicon;

fLanguage

English

Publisher

ieee

Conference_Titel

Radio Frequency integrated Circuits (RFIC) Symposium, 2005. Digest of Papers. 2005 IEEE

ISSN

1529-2517

Print_ISBN

0-7803-8983-2

Type

conf

DOI

10.1109/RFIC.2005.1489893

Filename

1489893