Force-observe, a new design for testability approach (CMOS VLSI circuits)

A technique called the force-observe approach (F-O) for eliminating hard-to-test or untestable nodes in CMOS technology is presented. This technique requires the addition of controllable and observable nodes to a circuit to improve the fault coverage as much as required. The F-O approach is characterized by a speed degradation smaller than the one introduced by other techniques. A formula to evaluate the area overhead of the F-O approach is proposed. It is shown that the area overhead is small for a complex VLSI circuit with a limited number of testability problems. This approach is very promising and, used in conjunction with the scan chain technique, it can be developed into a comprehensive solution to the problem of eliminating hard-to-test or untestable nodes from large VLSI designs.<>