DocumentCode
1591088
Title
A Novel Design of 1024-point Pipelined FFT Processor Based on Cordic Algorithm
Author
Shi Jiangyi ; Tian Yinghui ; Wang Mingxing ; Yang Zhe
Author_Institution
Dept. Microelectron., Xidian Univ., Xian, China
fYear
2012
Firstpage
80
Lastpage
83
Abstract
A novel ASIC design of a 1024-point pipelined FFT Processor is introduced in this paper. This is a new FFT architecture based on the radix-2 algorithm and cordic algorithm. The solution adopted in the design is used to achieve a high-frequency FFT processor of which the frequency could reach as high as 330MHz. It also shows an advantage in saving up to fifty percent hardware resources over traditional FFT processor.
Keywords
application specific integrated circuits; fast Fourier transforms; pipeline arithmetic; 1024-point pipelined FFT Processor; ASIC design; cordic algorithm; fast Fourier transforms; high-frequency FFT processor; radix-2 algorithm; Adders; Algorithm design and analysis; Computer architecture; Discrete Fourier transforms; Equations; Hardware; Signal processing algorithms; FFT; cordic; pepeline;
fLanguage
English
Publisher
ieee
Conference_Titel
Intelligent System Design and Engineering Application (ISDEA), 2012 Second International Conference on
Conference_Location
Sanya, Hainan
Print_ISBN
978-1-4577-2120-5
Type
conf
DOI
10.1109/ISdea.2012.503
Filename
6173152
Link To Document