• DocumentCode
    1591173
  • Title

    A technique to analyze the tolerance to transient overloads of a fault-tolerant real-time system

  • Author

    Bernat, Guillem ; Miro-Julia, Jose ; Proenza, Julian

  • Author_Institution
    Dept. de Matematiques i Inf., Univ. de les Illes Balears, Palma de Mallorca, Spain
  • fYear
    1997
  • Firstpage
    221
  • Lastpage
    226
  • Abstract
    Fault tolerance and real time computing have been traditionally considered as different domains. However, missing a deadline is a fault in a real time system. A real time fault tolerant architecture based on a redundancy executive (RX) is presented. The timing properties of such an executive are predictable. On this basis, a technique for predicting the temporal behaviour of a system, based on fixed priority schedulability analysis, is provided. Moreover this analysis can be applied to real time systems that present bounded transient overloads. In these systems the number of missed deadlines over a given period of time is bounded. The architecture, together with a dual time out scheme, masks both value errors and timing errors. Thus, providing a feasible mechanism for achieving fault tolerance for both the functional aspects and the timing aspects. Its application leads to cost effective systems because the resources do not have to be sized for the worst case and moreover, the response times are sometimes better than in the non fault tolerant equivalent system
  • Keywords
    real-time systems; redundancy; scheduling; software fault tolerance; bounded transient overloads; cost effective systems; dual time out scheme; fault tolerant real time system; feasible mechanism; fixed priority schedulability analysis; functional aspects; missed deadlines; non fault tolerant equivalent system; real time computing; real time fault tolerant architecture; redundancy executive; response times; temporal behaviour; timing aspects; timing errors; timing properties; transient overloads; value errors; Delay; Fault tolerance; Fault tolerant systems; Hardware; Real time systems; Redundancy; Timing; Transient analysis; Upper bound; Voting;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    High-Assurance Systems Engineering Workshop, 1997., Proceedings
  • Conference_Location
    Washington, DC
  • Print_ISBN
    0-8186-7971-9
  • Type

    conf

  • DOI
    10.1109/HASE.1997.648070
  • Filename
    648070