Title :
Macromodeling C- and RC-loaded CMOS inverters for timing analysis
Author_Institution :
Dept. of Electr. & Comput. Eng., American Univ. of Beirut, Lebanon
Abstract :
Timing macromodels for a CMOS inverter loaded by a capacitor or by a series-resistor shunt-capacitor circuit are derived and verified. The macromodel for the capacitive load case is a simple analytical function of a single variable which combines input wave shape, capacitive load, and transistor drive. The model for the RC case is a combination of lookup table and analytical function yielding excellent accuracy to within 5% of detailed circuit simulation
Keywords :
CMOS logic circuits; circuit analysis computing; integrated circuit modelling; logic CAD; logic gates; table lookup; timing; C-loaded CMOS inverters; RC-loaded CMOS inverters; capacitive load case; circuit simulation; input wave shape; lookup table; macromodels; series-resistor shunt-capacitor circuit; timing analysis; transistor drive; Capacitors; Circuit analysis; Circuit simulation; Delay; Integrated circuit interconnections; Inverters; Load modeling; Semiconductor device modeling; Table lookup; Timing;
Conference_Titel :
VLSI, 1996. Proceedings., Sixth Great Lakes Symposium on
Conference_Location :
Ames, IA
Print_ISBN :
0-8186-7502-0
DOI :
10.1109/GLSV.1996.497632
