DocumentCode
1591411
Title
FPGA verification of a single QC-LDPC code for 100 Gb/s optical systems without error floor down to BER of 10−15
Author
Chang, Deyuan ; Yu, Fan ; Xiao, Zhiyu ; Li, Yang ; Stojanovic, Nebojsa ; Xie, Changsong ; Shi, Xiaozhong ; Xu, Xiaogeng ; Xiong, Qianjin
Author_Institution
Network Res. Dept., Huawei Technol. Co., Ltd., Shenzhen, China
fYear
2011
Firstpage
1
Lastpage
3
Abstract
We present FPGA-based emulation results of a single QC-LDPC code with 20% redundancy designed for applications in 100 Gb/s optical transmission systems. Error floor-free transmission can be achieved at BER of 10-15 with a Q factor of 5.9 dB.
Keywords
cyclic codes; error statistics; field programmable gate arrays; forward error correction; optical communication; parity check codes; BER; FPGA verification; Q factor; QC-LDPC code; bit rate 100 Gbit/s; error floor-free transmission; optical transmission systems; Bit error rate; Complexity theory; Decoding; Field programmable gate arrays; Floors; Forward error correction; Parity check codes;
fLanguage
English
Publisher
ieee
Conference_Titel
Optical Fiber Communication Conference and Exposition (OFC/NFOEC), 2011 and the National Fiber Optic Engineers Conference
Conference_Location
Los Angeles, CA
ISSN
pending
Print_ISBN
978-1-4577-0213-6
Type
conf
Filename
5875607
Link To Document