Title :
Evaluation of multi-layered gate design on GME-TRC MOSFET for wireless applications
Author :
Malik, Priyanka ; Chaujar, Rishu ; Gupta, Mridula ; Gupta, R.S.
Author_Institution :
Dept. of Electron. Sci., Univ. of Delhi, New Delhi, India
Abstract :
In this paper, the impact of multi-layered gate design assimilation on Gate Material Engineered Trapezoidal Recessed Channel (GME-TRC) MOSFET has been studied for wireless applications in terms of linearity performance metrics, using device simulators: ATLAS and DEVEDIT, and compared with conventional Trapezoidal Recessed channel (TRC) and GME-TRC MOSFETs. Simulation study reveals that GME-TRC MOSFET with Multi-Layered Gate implementation significantly enhances the linearity performance in comparison with conventional TRC-MOSFET and GME-TRC MOSFET in terms of figure of merit (FOM) metrics: VIP2, VIP3, IIP3 and higher order transconductance coefficients: gm1, gm2, gm3, thus proving its efficacy for high performance wireless applications.
Keywords :
MOSFET; radio equipment; ATLAS; DEVEDIT; GME-TRC MOSFET; gate material engineered trapezoidal recessed channel MOSFET; linearity performance metrics; multilayered gate design; wireless application; Design engineering; Dielectric devices; High K dielectric materials; High-K gate dielectrics; Hot carrier effects; Linearity; MOSFET circuits; Power engineering and energy; Transconductance; Tunneling;
Conference_Titel :
Semiconductor Electronics (ICSE), 2010 IEEE International Conference on
Conference_Location :
Melaka
Print_ISBN :
978-1-4244-6608-5
DOI :
10.1109/SMELEC.2010.5549492
