Application decomposition for high-speed network processing platforms

The rapid advancements in optical networking have increased the capacity of physical links. As an alternative to the ASIC or generic microprocessor-based approaches, new semiconductor devices have emerged, called network processors (NP), optimised to provide programmable processing of protocol data units in networks with diverse requirements for current and emerging protocols and services. In this paper we present a NP architecture that targets the tight coupling of software and hardware for the efficient execution of telecommunication protocols. The proposed architecture is based on a high-performance RISC core, which is extended with reconfigurable, pipelined hardware. Additionally, we discuss the application spectrum of the proposed NP and describe a statefull-inspection application for an IP-firewall system. To identify time-critical operations, CPU-consuming functions and the common execution path pertaining to the statefull-inspection application, extensive protocol profiling has been performed resulting in an efficient SW/HW partitioning of the application on the proposed NP platform. The analysis performed concludes that the described protocol processor can sustain demanding protocol processing up to the transport layer for multiple Gbits/sec of incoming network traffic.