DocumentCode
1592265
Title
A technique for the reduction of harmonic distortion and power losses in advanced static VAr compensators
Author
Chen, Z. ; Tennakoon, S.B.
Author_Institution
Sch. of Eng. & Comput. Sci., Durham Univ., UK
Issue
0
fYear
1995
Firstpage
620
Abstract
The harmonic reduction technique presented is suitable for the application to advanced static VAr compensators (ASVC). The technique is combined with a soft switching strategy to reduce the low order harmonics and the switching losses. The theoretical basis is established and the effectiveness of the method is investigated by simulation and experiment. Both hard switched and soft switched ASVCs are considered. Theoretical and experimental results show good agreement
Keywords
circuit testing; harmonic distortion; losses; network analysis; power system harmonics; static VAr compensators; switching circuits; advanced static VAr compensators; harmonic distortion; low order harmonics; power losses; simulation; soft switching strategy; switching losses; testing; Capacitors; Circuits; Frequency; Harmonic distortion; Power system harmonics; Reactive power; Static VAr compensators; Static power converters; Switching loss; Voltage control;
fLanguage
English
Publisher
ieee
Conference_Titel
Applied Power Electronics Conference and Exposition, 1995. APEC '95. Conference Proceedings 1995., Tenth Annual
Conference_Location
Dallas, TX
Print_ISBN
0-7803-2482-X
Type
conf
DOI
10.1109/APEC.1995.469085
Filename
469085
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