Title :
An efficient multiple scan chain testing scheme
Author :
Zhang, Zaifu ; McLeod, Robert D.
Author_Institution :
Dept. of Electr. & Comput. Eng., Manitoba Univ., Winnipeg, Man., Canada
Abstract :
In this paper an improved multiple scan chain testing scheme to enhance stuck-at and delay fault testing is proposed. With judicial selection of taps from an n stage CA generator, correlation within a multiple input scan chain is reduced. Adopting the multiple scan chains fed by the selected taps of the CA generator also eases the difficulty of arranging shift register latches (SRLs) for scan based pseudo-exhaustive stuck-at fault testing
Keywords :
automatic testing; boundary scan testing; cellular automata; delays; fault diagnosis; integrated circuit testing; logic testing; shift registers; delay fault testing; multiple input scan chain; multiple scan chain testing scheme; n stage CA generator; pseudo-exhaustive fault testing; shift register latches; stuck-at fault testing; Built-in self-test; Circuit faults; Circuit testing; Content addressable storage; Delay; Design for testability; Integrated circuit testing; Shift registers; System testing; Very large scale integration;
Conference_Titel :
VLSI, 1996. Proceedings., Sixth Great Lakes Symposium on
Conference_Location :
Ames, IA
Print_ISBN :
0-8186-7502-0
DOI :
10.1109/GLSV.1996.497636
