An efficient clustering technique for circuit partitioning

As the complexity of VLSI circuits increases, a hierarchical design approach becomes essential to shorten the design period. Circuit clustering plays a fundamental role in hierarchical designs. Identifying strongly connected components in the netlist can significantly reduce the complexity of the circuit and improve the performance of the design process. A good clustering method should identify groups of cells which will eventually end up together in the final partitioning and placement stages. The sizes of today´s circuits are so large that a top-down partitioning scheme alone is infeasible. Therefore, an effective bottom-up clustering approach is necessary as a preprocessing stage in a hierarchical placement approach. In this paper, new clustering techniques that can be used for circuit partitioning and placement are introduced