Enhanced Performance and SRAM Stability in FinFET with Reduced Process Steps for Source/Drain Doping

Improved static noise margin in SRAM of 18% and decreased intrinsic inverter delay of 6% is demonstrated for the first time in double-gate CMOS finFET with gate- source/drain underlap doping. The excellent results are achieved by optimization of the spacer while simplifying the processing of source/drain region by skipping costly implants. Improved circuit and device performance with reduced processing steps make finFETs a more attractive option for 32 nm technology node and beyond.