Title :
Enhanced Performance and SRAM Stability in FinFET with Reduced Process Steps for Source/Drain Doping
Author :
Yang, J.W. ; Harris, H.R. ; Hussain, M.M. ; Sassman, B. ; Tseng, H.-H. ; Jammy, R.
Author_Institution :
SEMATECH, Austin, TX
Abstract :
Improved static noise margin in SRAM of 18% and decreased intrinsic inverter delay of 6% is demonstrated for the first time in double-gate CMOS finFET with gate- source/drain underlap doping. The excellent results are achieved by optimization of the spacer while simplifying the processing of source/drain region by skipping costly implants. Improved circuit and device performance with reduced processing steps make finFETs a more attractive option for 32 nm technology node and beyond.
Keywords :
CMOS memory circuits; MOSFET; SRAM chips; semiconductor doping; SRAM; double-gate CMOS finFET; gate drain underlap doping; gate source underlap doping; spacer; static noise margin; CMOS technology; Circuits; Delay effects; Doping; FinFETs; Implants; Inverters; Random access memory; Space technology; Stability;
Conference_Titel :
VLSI Technology, Systems and Applications, 2008. VLSI-TSA 2008. International Symposium on
Conference_Location :
Hsinchu
Print_ISBN :
978-1-4244-1614-1
Electronic_ISBN :
1524-766X
DOI :
10.1109/VTSA.2008.4530779
