BEOL Advance Interconnect Technology Overview and Challenges

Author

Hsia, Liang Choo ; Tan, Juan Boon ; Zhang, Bei Chao ; Liu, Wu Ping ; Lim, Yeow Kheng ; Sohn, Dong Kyun

Author_Institution

Chartered Semicond. Manuf. Ltd., Singapore

fYear

2008

Firstpage

28

Lastpage

29

Abstract

An overview of the semiconductor roadmap of interconnects process transition from 0.13mum to 45nm using current proven state- of-the-art manufacturing technology in relation to the integration of dielectric material progressing from fluorinated silica glass to porous low-k will be discussed. Key challenges of process integration with shrinking dimension to meet the ever-demanding timing delay due to interconnects will be shown. Process enhancements with design for manufacturing concepts are addressed to meet the industrial specifications of reliability and chip package interaction for mass production.

Keywords

dielectric materials; glass; integrated circuit interconnections; integrated circuit manufacture; BEOL advance interconnect technology; dielectric material; fluorinated silica glass; interconnects process transition; semiconductor roadmap; size 0.13 mum; size 45 nm; Delay; Dielectric materials; Glass manufacturing; Industrial relations; Manufacturing industries; Manufacturing processes; Process design; Semiconductor device manufacture; Silicon compounds; Timing;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology, Systems and Applications, 2008. VLSI-TSA 2008. International Symposium on

Conference_Location

Hsinchu

ISSN

1524-766X

Print_ISBN

978-1-4244-1614-1

Electronic_ISBN

1524-766X

Type

conf

DOI

10.1109/VTSA.2008.4530783

Filename

4530783