A Study of Slow Erasing Speed at Edge Cell in Nano-Scale NAND Flash Memory

Author

Wang, Hsin-Heng ; Huang, Chiu-Tsung ; Chen, Shin-Hsien ; Kuo, Ricky ; Liu, Sophia ; Yang, Ling-Kuey ; Wei, Houng-Chi ; Pittikoun, Saysamone ; Shirota, Riichiro ; Cho, Chin-chen

Author_Institution

Powerchip Semicond. Corp., Hsinchu

fYear

2008

Firstpage

87

Lastpage

88

Abstract

In this paper, we present our study of a method to improve nonuniform erasing speeds caused by slow edge cells (cell 0 and cell 31). Simulation and measurement results showed that the slow erasing speed at edge cells is resulted from the coupling effect of select gate (SG) transistors. Moreover, several extra bias voltages were forced on the pass wordlines to evaluate the electrostatic potential difference and to improve erase uniformity. Simulation result and measurement data demonstrated that 0.4 V of the extra bias voltage can improve the uniformity of the erasing speed in nano-scale NAND flash memory.

Keywords

NAND circuits; electrostatics; flash memories; nanotechnology; bias voltage; electrostatic potential difference; nanoscale NAND flash memory; select gate transistors; slow edge cells; slow erasing speed; voltage 0.4 V; Circuit testing; Costs; Electrostatic measurements; Flash memory; Manufacturing; Nonvolatile memory; Parasitic capacitance; Semiconductor device noise; Velocity measurement; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology, Systems and Applications, 2008. VLSI-TSA 2008. International Symposium on

Conference_Location

Hsinchu

ISSN

1524-766X

Print_ISBN

978-1-4244-1614-1

Electronic_ISBN

1524-766X

Type

conf

DOI

10.1109/VTSA.2008.4530811

Filename

4530811