Optimal PD-SOI Technology for High Performance Applications

We present an optimal partially-depleted silicon-on-insulator (PD-SOI) platform, which demonstrates superior performance of SOI over bulk technology. Device optimization is performed in terms of circuit switch speed and power consumption through channel and S/D engineering. Fundamental device characteristics, SRAM yields, reliability assessment, and physical IP qualification for our PD-SOI platform are all validated to demonstrate the feasibility for high performance applications. Performance comparison based on circuit simulation clearly shows the SOI advantage on area and power consumption. In addition, the strained-SOI (sSOI) technology is developed for further SOI performance enhancement.